CC-100 PowerOp IP
The CC-100 PowerOp IP Proof-of-Concept silicon originally was produced on IBM CM018RF RF. The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, and is also available on request from CurrentRF Proof-of- concept, Characterization. And Design Aids for the CC-100 IP are available on this page.
The CC_100_IP_Proof_of_Concept_and Characterization.pdf shows the Proof-of-Concept Silicon performance with a BIST engine of ten logic gates providing the on-board noise generator for the IP. The CC_100_IP_Structure and Design Aid.pdf shows the unique way that this IP fits into mixed signal and digital designs, what it can do to lower power dissipation in host designs, and shows the predictive capability and procedures needed for successful IP integration into mixed signal and digital chips.